Publications

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2008

SBAC-PAD "Hiding Communication Delays in Clustered Microarchitectures"
Robert LaDuca, Joseph Sharkey and Dmitry Ponomarev
to appear in the 20th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campo Grande, Brasil, October 2008.

SBAC-PAD "Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch Signatures"
Balaji Vijayan and Dmitry Ponomarev
to appear in the 20th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campo Grande, Brasil, October 2008.

SBAC-PAD "Aggressive Scheduling and Speculation in Multithreaded Architectures: Is It Worth Its Salt?"
Jason Loew and Dmitry Ponomarev
to appear in the 20th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campo Grande, Brasil, October 2008.

ICPP "Two-Level Reorder Buffers: Accelerating Memory-bound Applications on SMT Architectures"
Jason Loew and Dmitry Ponomarev
to appear in the 37th International Conference on Parallel Processing (ICPP), September 2008.

TACO "Reducing Register Pressure in SMT Processors through L2-Miss-Driven Early Register Release"
Joseph Sharkey, Jason Loew, Dmitry Ponomarev
To appear in the ACM Transactions on Architecture and Code Optimization (ACM TACO), 2008 .

TC "Predicting and Exploiting Transient Values for Reduced Register File Pressure and Energy Consumption"
Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose
IEEE Transactions on Computers, Vol.57, No 1, January 2008, pp.82-95.

TVLSI "Selective Writeback: Reducing Register File Pressure and Energy Consumption"
Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No 6, June 2008, pp.650-661.

2007

ICS "An L2-Miss-Driven Early Register Deallocation for SMT Processors"
Joseph Sharkey, Dmitry Ponomarev
21st ACM International Conference on Supercomputing (ICS'07), Seattle, WA, June 2007.

TC "Exploiting Operand Availability for Efficient Simultaneous Multithreading"
Joseph Sharkey, Dmitry Ponomarev
IEEE Transactions on Computers, Vol. 55, No 2., February 2007, pp.208-223.

2006

HiPC

"Trade-offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors"
Joseph Sharkey, Nayef Abu-Ghazaleh, Dmitry Ponomarev, Kanad Ghose and Aneesh Aggarwal
13th IEEE International Conference on High-Performance Computing (HiPC'06), Bangalore, India, December 2006, pp.135-147.

PACT "Adaptive Reorder Buffers for SMT Processors"
Joseph Sharkey, Deniz Balkan, Dmitry Ponomarev
15th IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT'06),
Seattle, WA, September 2006, pp.244-253.

PACT "SPARTAN: Speculative Avoidance of Register Allocations to Transient Values for Performance and Energy-Efficiency"
Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose
15th IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT'06)
Seattle, WA, September 2006, pp.265-274.

ISLPED "Selective Writeback: Exploiting Transient Values for Performance and Energy-Efficiency"
Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose
IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'06),
Tegernsee, Germany, October 2006.

ICPP "Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch"
Joseph Sharkey and Dmitry Ponomarev
35th International Conference on Parallel Processing (ICPP'06), Columbus OH, August 2006, pp.329-336.

ICPP "Address-Value Decoupling for Early Register Deallocation"
Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev and Aneesh Aggarwal
35th International Conference on Parallel Processing (ICPP'06), Columbus OH, August 2006, pp.337-343.

ASGI "Exploiting Short-Lived Values for Low-Overhead Transient Fault Recovery"
Nayef Abu-Ghazaleh, Joseph Sharkey, Dmitry Ponomarev and Kanad Ghose
to appear in Workshop on Architectural Support for Gigascale Integration (ASGI'06),
held in conjunction with ISCA-33, Boston, MA, June 2006.

HPCA "Efficient Instruction Schedulers for SMT Processors"
Joseph Sharkey and Dmitry Ponomarev
12th International Symposium on High Performance Computer Architecture (HPCA-12) , Austin TX, February 2006, pp.303-313.

TACO "Instruction Packing: Toward Fast and Energy-Efficient Instruction Scheduling"
Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin
ACM Transactions on Architecture and Code Optimization (ACM TACO), vol.3, No 2, June 2006, pp.156-181.

TC "Early Register Deallocation Mechanisms Using Checkpointed Register Files"
Oguz Ergin, Deniz Balkan, Dmitry Ponomarev, Kanad Ghose
IEEE Transactions on Computers, vol.55, No 9, pp.1153-1166, September 2006.

TC "Dynamic Resizing of Superscalar Datapath Components for Energy-Efficiency"
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
IEEE Transactions on Computers, Volume 55, No.2, February 2006, pp.199-213.

2005

IEE CDT

"Reducing the Power Dissipation of Register Alias Tables in High Performance Processors"
Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
IEE Proceedings, Computer and Digital Techniques, Volume 152, Issue 6, November 2005, pp.739-746.

IBM P=AC2

"Scalable, Low-Complexity Instruction Schedulers for SMT Processors"
Joseph Sharkey, Deniz Balkan, Dmitry Ponomarev
2nd IBM Watson Conference on the Interaction between Architecture, Circuits and Compilers (P=ac2), October 2005.

ICCD

"Power-Efficient Wakeup Tag Broadcast"
Joseph Sharkey, Kanad Ghose, Dmitry Ponomarev, Oguz Ergin
23rd IEEE International Conference on Computer Design (ICCD'05) , San Jose, CA, October 2005.

EURO-PAR

"Non-Uniform Instruction Scheduling"
Joseph Sharkey, Dmitry Ponomarev
11th International ACM/IEEE Euro-Par Conference , Lisbon, Portugal, August-September 2005. Acceptance rate - 31%

EURO-PAR

"Instruction Recirculation: Eliminating Counting Logic in Wakeup Free Schedulers"
Joseph Sharkey, Dmitry Ponomarev
11th International ACM/IEEE Euro-Par Conference , Lisbon, Portugal, August-September 2005. Acceptance rate - 31%

ISLPED

"Instruction Packing: Reducing Power and Delay of the Dynamic Scheduling Logic"
Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin
IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'05) , San Diego, CA, August 2005.
Acceptance rate for full papers - 9%

2004

MICRO

"Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure"
Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry Ponomarev
37th IEEE/ACM International Symposium on Microarchitecture (MICRO-37) , Portland, OR, December 2004.

TC	"Energy-Efficient Comparators for Superscalar Datapaths" Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose IEEE Transactions on Computers, vol.53, No. 7, July 2004, pp.892-904.

TC	"Isolating Short-Lived Operands for Energy Reduction" Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose IEEE Transactions on Computers, vol. 53, No. 6, June 2004, pp. 697-709.

TC	"Complexity-Effective Reorder Buffer Designs for Superscalar Processors" Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad Ghose IEEE Transactions on Computers, vol.53, No. 6, June 2004, pp.653-665.

PACS

"Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization"
Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin
4th Workshop on Power-Aware Computer Systems (PACS), held in conjuncton with the
37th IEEE/ACM International Symposium on Microarchitecture (MICRO-37) , Portland, OR, December 2004.

IBM P=AC2

"Selective Writeback: Improving Processor Performance and Energy-Efficiency"
Deniz Balkan, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
1st Watson Conference on Interaction between Architecture, Circuits and Compilers (P=ac2 conference),
IBM Research Center at Yorktown Heights, October 2004, pp.171-180.

VPW2

"Predicting, Detecting and Exploiting Transient Values"
Deniz Balkan, Dmitry Ponomarev, Kanad Ghose
2nd Value Prediction and Value-based Optimization Workshop, in conjunction with ASPLOS-XI , October 2004, pp.18-25.

ICCD

"Increasing Processor Performance Through Early Register Release"
Oguz Ergin, Deniz Balkan, Dmitry Ponomarev, Kanad Ghose
22nd IEEE International Conference on Computer Design (ICCD'04) , October 2004, pp.480-487.

2003

TVLSI

"Energy-Efficient Issue Queue Design"
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose, Peter Kogge
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, No 5, October 2003, pp. 789-800.

ICCD

"Distributed Reorder Buffer Schemes for Low Power"
Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
21st IEEE International Conference on Computer Design (ICCD'03) , San Jose, CA, October 2003, pp.364-370.

PACT

"Reducing Datapath Energy Through the Isolation of Short-Lived Operands"
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
12th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT'03) , New Orleans, September 2003, pp.258-268.

ISLPED

"Reducing Reorder Buffer Complexity Through Selective Operand Caching"
Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad Ghose
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED'03) , Seoul, South Korea, August 2003, pp. 235-240.

ISLPED

"Power Efficient Comparators for Long Arguments in Superscalar Processors"
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED'03) , Seoul, South Korea, August 2003, pp. 378-383.

PATMOS

"Energy Efficient Register Renaming"
Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'03), Torino, Italy, September 2003. Published as Lecture Notes in Computer Science (LNCS 2799), pp.219-228, Springer-Verlag.

2002

ICCD

"A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors"
Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev
20th IEEE International Conference on Computer Design (ICCD'02) , Freiburg, Germany, September 2002, pp.118-121.

PATMOS

"Energy-Efficient Design of the Reorder Buffer"
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
12th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'02) Seville, Spain, September 2002. Published as Lecture Notes in Computer Science, vol. 2451, pp.289-299, Springer-Verlag.

ICS

"Low-Complexity Reorder Buffer Architecture"
Gurhan Kucuk, Dmitry Ponomarev, Kanad Ghose
16th ACM International Conference on Supercomputing (ICS'02), New York, June, 2002, pp. 57-66.

DATE

"AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors"
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
5th Design, Automation and Test in Europe Conference (DATE'02), Paris, France, March 2002, pp. 124-129.

2001

MICRO "Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources"
Dmitry Ponomarev, Gurhan Kucuk and Kanad Ghose
34th IEEE/ACM International Symposium on Microarchitecture (MICRO-34), December 2001, pp. 90-101.

ISLPED "Energy-Efficient Instruction Dispatch Buffer Design for Superscalar Processors"
Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev, Peter Kogge
IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'01), Huntington Beach, USA, August 2001, pp. 237-242.

EURO-PAR "Optimal Polling for Latency-Throughput Tradeoffs in Queue-Based Network Interfaces for Clusters"
Dmitry Ponomarev, Kanad Ghose, Eugeny Saksonov
7th ACM Euro-Par Conference, Manchester, UK. Published as LNCS 2150, Springer-Verlag, August 2001, pp.86-95.

WCED "Dynamic Allocation of Datapath Resources for Low Power"
Dmitry Ponomarev, Gurhan Kucuk and Kanad Ghose,
Workshop on Complexity-Effective Design (WCED'01), 28th International Symposium on Computer Architecture (ISCA-28), Goteborg, Sweden, June 2001

IWIA "Power Reduction in Superscalar Datapaths Through Dynamic Bit-Slice Activation"
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
International Workshop "Innovative Architecture for Future Generation High-Performance Processors and Systems" (IWIA'01), January 2001, pp.16-24. Invited paper

2000 and before

KOOLCHIPS "Exploiting Bit-Slice Inactivities for Reducing Energy Requirements of Superscalar Processors"
Kanad Ghose, Dmitry Ponomarev, Gurhan Kucuk, Andrew Flinders, Peter M.Kogge, Nikzad Toomarian
Kool Chips Workshop, 33rd International Symposium on Microarchitecture ( MICRO-33), Monterey, CA, December 2000.

HIPC "A Comparative Study of Some Network Subsystem Organizations"
Dmitry Ponomarev and Kanad Ghose
5th IEEE/ACM International Conference on High Performance Computing (HiPC 98), Chennai, India, December 1998, pp. 436-443.

ISAS "Bounded Error Estimate Model of System States Computations for General Service Order Polling Scheme"
Eugeny Saksonov and Dmitry Ponomarev
Proceedings of the Int'l. Conf. on Information Systems Analysis and Synthesis, (ISAS'96) July 1996, pp.791-796.

"Exact Joint Queue Length Distribution for the Exhaustive Polling"
Eugeny Saksonov and Dmitry Ponomarev
Advances in Artificial Intelligence and Engineering Cybernetics, Vol.III, published by the International Institute for Advanced Studies in Systems Research and Cybernetics, Baden-Baden, Aug. 1996, pp.149-153.

Order Dependency in a Single Server Cyclic M/G/1 Multiqueue System Performance"
Eugeny Saksonov, Dmitry Ponomarev and Sam Sengupta,
Advances in Systems Studies, published by the International Institute for Advanced Studies in Systems Research and Cybernetics, Baden-Baden, Germany, August 1995, pp.54-58.

"Estimation of Systems States in a Single Server M/G/1 Multiqueue System in a Cyclic Access Scheme"
Eugeny Saksonov, Dmitry Ponomarev and Sam Sengupta,
Advances in Computer Cybernetics, vol.III, published by the International Institute for Advanced Studies in Syst. Research and Cybernetics, Baden-Baden, Germany, August 1995, pp.49-53