Tameesh Suri

Email: <firstname> [at] cs [dot] binghamton [dot] edu
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I graduated with a PhD in Electrical Engineering from State University of New York, Binghamton in May 2010 (although I defended in Summer 2009). Previously, I received a BEng (Hons) degree in Electronics Engineering and MS in Electronic and Computer Engineering from the University of Birmingham, United Kingdom. I focused on Computer architecture during my graduate studies, with specific emphasis on adaptive core micro-architectures. Parts of this work received a Best Paper Award at the 15th IEEE/ACM International Conference on High Performance Computing and a Best Student Paper Award at the 22nd IEEE International Conference on VLSI Design. I was also fortunate to recieve the Distinguished Dissertation Award at Binghamton in 2010 (Letter, Awardee list). (complete list of awards)

I currently work at Intel Corporation on next-generation CPU and datacenter architectures. Previously, I worked in the Systems Architecture Lab at Samsung Semiconductor, Inc. investigating systems architecture and performance for data center and hyper scale applications.


In the past, I have worked as a computer performance architect at Intel Corporation (2010-2014) in IDG architecture group. Specifically, I worked on multi-generational Server SoC products, more commonly referred as micro-servers (C2000, (14nm next-gen)). I was the lead performance architect on next generation 14nm Server SoC, and led multiple innovations in the uncore and memory controller architectures. Back in 2009, I worked as a CPU architect at Soft Machines, Inc (stealth CPU startup) in the bay area, investigating some very innovative architectures [1, 2].


Publications


Tameesh Suri, Aneesh Aggarwal: Adaptive and Scalable Predictive Page Policies for High Core-Count Server CPUs. [pdf] 8th ACM International Conference on Architecture of Computing Systems (ARCS), April 2017


Quimin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Tameesh Suri, Manu Awasthi, Zvika Guz, Anahita Shayesteh and Vijay Balakrishnan: Performance Analysis of NVMe SSDs and their Implication on Real World Databases. [pdf] 8th ACM International System and Storage Conference (SYSTOR), May 2015


Quimin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Manu Awasthi, Tameesh Suri, Anahita Shayesteh, Zvika Guz and Vijay Balakrishnan: Performance Characterization of Hyperscale Applications on NVMe SSDs. [pdf] ACM SIGMETRICS, June 2015 (poster)


Qiumin Xu, Mrinmoy Ghosh, Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayesteh, Vijay Balakrishnan: Performance Characterization of Hyperscale Applications on NVMe SSDs. [poster] 6th Annual Non-Volatile Memories Workshop (NVMW 2015), March 2015 (poster)


Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayesteh, Mrinmoy Ghosh, Vijay Balakrishnan: System-Level Characterization of Datacenter Applications. [pdf] 6th ACM/SPEC International Conference on Performance Engineering (ICPE'15), January 2015 (Best Paper Award)


Zvika Guz, Manu Awasthi, Vijay Balakrishnan, Mrinmoy Ghosh, Anahita Shayesteh, Tameesh Suri: Real-time Analytics as the Killer Application for Processing-In-Memory.[pdf] 2nd Workshop on Near-Data Processing (WonDP), in conjunction with the 47th IEEE/ACM International Symposium on Microarchitecture (MICRO-47), Dec 2014


Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazaleh, Tameesh Suri: SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors. [pdf] IEEE Transactions on Computers 63(2): 484-496 (2014)


Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazaleh, Tameesh Suri: SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors. [pdf] 8th Annual ACM International Conference on Computing Frontiers (CF'11), May, 2011


Tameesh Suri, Aneesh Aggarwal: Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration. [pdf] International Journal of Parallel Programming 38(3-4): 203-224 (2010)


Tameesh Suri, Aneesh Aggarwal Improving Performance of Simple Cores by Exploiting Loop-Level Parallelism through Value Prediction and Reconfiguration. [pdf] 6th Annual ACM International Conference on Computing Frontiers (CF'09), May, 2009

Tameesh Suri, Aneesh Aggarwal Improving Scalability and Per-core Performance in Multi-cores through Resource Sharing and Reconfiguration. [pdf] 22nd Annual IEEE International Conference on VLSI Design (VLSID'09), January, 2009 (Best Student Paper Award)

Tameesh Suri, Aneesh Aggarwal Scalable Multi-cores with Improved Per-core Performance using Off-the-critical Path Reconfigurable Hardware. [pdf] 15th Annual IEEE/ACM International Conference on High Performance Computing (HiPC'08), December, 2008 (Best Paper Award)

Tameesh Suri Improving Instruction Level Parallelism through Reconfigurable Units in Superscalar Processors.[pdf] ACM SIGARCH Computer Architecture News, Volume 35 , Issue 3, June 2007



Patents


Prediction based DRAM policies., Aneesh Aggarwal and Tameesh Suri, USPTO granted patent US 9,378,127

High bandwidth peer-to-peer switched key-value caching., Tameesh Suri and Manu Awasthi, USPTO granted patent US 9,723,071

Computing system with parallel mechanism and method of operation thereof., Tameesh Suri, Manu Awasthi, Mrinmoy Ghosh, USPTO pending patent 14/674,399

Dynamic Garbage Collection P/E policies for redundant storage blocks and distributed soft- ware stacks., FNU Suhas, Ashwini Batrahalli, Tameesh Suri, US Patent App. 62/286,926

Block versioning to acheive consistent and predictable SSD performance., Arash Rezaei, Tameesh Suri, Bob Brennan, US Patent App. 15/133,205

Multi-bit data representation framework to enable dual program operation on solid-state flash devices., Narges Shahidi, Tameesh Suri, Manu Awasthi, Vijay Balakrishnan, USPTO application filed US 62/341,584

BLOCK CLEANUP: Page reclamation process to reduce garbage collection overhead in dual-programmable NAND flash devices. Narges Shahidi, Manu Awasthi, Tameesh Suri, Vijay Balakrishnan. Application filed with USPTO