Richard R. Eckert and James L. Antonakos
As an integral part of an advanced computer science course
in microcomputer systems it was thought that students could benefit from
the design of a single board computer system based on a readily available
microprocessor. This led to the project that is described in this paper.
Most of the actual design work was done by James Antonakos as part of an
Independent Study project. The result was a single board microcomputer
system (SBMCS) that requires only a power supply and a serial monitor to
be fully functional. This same project will be assigned to advanced undergraduate
and intermediate graduate computer science students working in teams. A
photograph of the working single board microcomputer system that was designed
and constructed is given in Figure 1.
Figure 1. A photograph of the SBMCS.
8088 Single Board Microcomputer System Hardware
The purpose of this document is to briefly describe the theory of operation behind the 8088 Single Board Microcomputer. The system has been designed to meet the following requirements:
1) A sufficiently large memory (both RAM and ROM)
2) Parallel i/o capabilities
3) Serial i/o capabilities
4) Analog i/o capabilities
5) A maximum mode system
A block diagram of the system showing the functional relationships between the various parts of the system is given in Figure 2.
Figure 2. A block diagram of the SBMCS.
The descriptions that follow are based on the 4-page schematic for the system. Page one is the schematic of the CPU section, containing the 8088, an 8284 clock generator, an 8288 bus controller and address and data line buffers. The 8284 is needed to generate the clock, ready and reset signals. The 8088 may be placed into a non-ready state by grounding either of the RDY inputs on the 8284. Figure 3 shows the schematic diagram of the CPU module.
Figure 3. A schematic of the SBMCS’s CPU module.
The 8288 is needed to decode the 8088's status outputs since we are operating the 8088 in maximum mode. In addition to generating the memory and io-port read/write signals the 8288 also controls the bidirectional data bus driver (the 8286) and the lower address latch chip (the 8282). Since the upper address lines are not multiplexed all we need to do is buffer them, hence the use of the LS244 octal buffer. Buffering the address and data lines is very important if future expansion of the system memory or i/o spaces is desired. By itself the 8088 is able to drive a few TTL loads but the drivers provide it with the ability to drive many more loads. Figure 3 shows the schematic of the CPU module
The second page of schematics is the MEMORY section. This section contains 8K bytes of RAM and 8K bytes of EPROM. The EPROM used is a 2764. Address lines A0 through A12 are used to select one of 8192 locations inside the EPROM. Its data lines are active whenever both of its enables are low. OE is controlled by the systems MRDC signal (memory read command) and CS is low whenever address lines A13, A14 and A15 are all high (via output 7 of the LS138). This addressing scheme will give an address range for the EPROM from E000 to FFFF. The EPROM must be in high memory because of the power-on instruction fetch sequence. Figure 4 shows the schematic diagram of the MEMORY module.
Figure 4. A schematic of the SBMCS’s MEMORY module
The 6264 RAM operates much in the same way, the exceptions being the addition of the MWTC (memory write command) signal and the connection between CS and output 0 of the LS138, which is active whenever the address bus is in the range 0000 to 1FFF. The LS138 provides 6 more outputs for mapping 8K sections into the first segment.
Page three of the schematics shows the I/O section, where 24 parallel i/o lines and a serial i/o line are made available. The LS138 is used to map out 8 separate i/o port areas, the first at 00 and the 8th at E0. These port addresses reflect the state of address lines A5, A6 and A7. Port-bank 00 controls the analog section circuitry. Port-bank 20 is for the 8255 generating 24 parallel i/o lines and bank 40 is used for the 8251 serial chip. Both peripherals (the 8255 and the 8251) are connected to the data bus and make use of the i/o read/write command signals IORC and IOWC. In the case of the 8255 two address lines (A0 and A1) are used to address the internal circuitry of the 8255. The 8251 requires only one address line (A0) for control. The BAUD rate is controlled both by the software used to initialize the 8251 and also by the frequency output of the 1411 oscillator/divider. The serial data lines are converted from TTL to RS232C and back by the 1488/89 line driver/receivers.
Figure 5. A schematic of the SBMCS’s I/O module.
The last page of schematics (Figure 6) details the ANALOG I/O section. Here a second 8255 is used to generate the required signals for the 0804 ADC and to transfer data between the system and the 1408/0804 data lines. The 1408 is an 8-bit Digital to Analog converter set up to sink from 0 to 1 mA at its output. This current controls a current to voltage converter made from a 741 op-amp which converts the current to a voltage level somewhere between -2.5 and +2.5 volts.
Figure 6. A schematic of the SBMCS’s Analog I/O module
The 0804 is an 8-bit Analog to Digital converter. The conversion time is based largely on the change in voltage input from the last conversion and also the size of the timing components (the 10K resistor and 150 pF capacitor). Since the 0804 will not convert a negative voltage a second 741 circuit is used as a level shifter, adding a 2.5V DC offset to the applied voltage. On the 0804 a conversion is started by bringing its WR line low and data may be read at the end of conversion (INT output goes low) by bringing its RD line low. The fastest conversion time possible in this configuration is roughly 125 uSec. This means that the converter will not accurately reproduce waveforms with frequencies exceeding a few hundred Hertz.
All in all the 8088 system represents a flexible tool
that may be easily built with a minimum of parts and expanded at a later
time without having to change any of the existing hardware.
The following provides information related to the software operation of the 8088 Single Board Microcomputer System.
The heart of this software is a simple system monitor (primitive operating system) that has been programmed into the 2764 EPROM memory. Details are given in the section on the system monitor, below.
The 8088 CPU runs from an 8284 driven by a 10 MHz crystal.
EPROM: 2764 8K-bytes, E000 to FFFF
RAM: 6264 8K-bytes, 0000 to 1FFF
PARALLEL I/O: Two 8255's
Analog: port A (00) drives a 1408 DAC
port B (01) reads the 0804 ADC
port C (02) controls the 0804
Control port (03)
Digital port A (20)
port B (21)
port C (22)
Control port (23)
SERIAL I/O: 8251 with 1488/89 line driver/receivers
port (40) data
port (41) Control/Status
Since the 8088 will execute its first instruction starting at address FFFF0 the equivalent address in our system is FFF0 because we ignore the upper 4 address lines. This address corresponds to address 1FF0 in the EPROM and starting at this location is the following code:
EA 00 01 00 0E
which performs a long jump to the start of the monitor
(EPROM address 100, CS equal to 0E00).
Using the System Monitor
This section gives details on the usage of the 15 monitor commands designed for use with the 8088 Single Board ComputerSystem. Commands may be entered in upper or lower case but no editing of the command line is allowed. Operands for the commands (either hex addresses or hex data) may also be entered in either upper or lower case as well. If a mistake is made during entry of the number the monitor will issue a '?' with a beep and the user must then retype the entire number. If more than 4 hex characters are entered only the last 4 (or last 2 in some cases) will be used.
Here then is a simple summary of the commands and their use:
B - set breakpoint
This command is used to specify the address where the user program should break away from its execution and return to the monitor. Breakpoints are very useful when debugging a program.
C - clear breakpoint
Clears the saved breakpoint address. This command must be used before attempting to set a new breakpoint. Also, the breakpoint is automatically cleared when it is encountered in the user program.
D - dump memory contents
Displays memory as hexadecimal pairs on 16-byte lines. The starting and ending addresses of the memory area to be dumped are supplied by the user.
E - enter new register data
Allows data to be changed in the internal register storage area of the monitor. All processor registers may be altered, but only the first 7 are loaded prior to the jump to user code.
G - go execute a user program
The system fetches its next instruction from the user program loaded at the address specified in the command.
H - display help message
A brief help message is display showing the syntax and use of each monitor command.
I - input data from port
Input and display the byte at the input port specified by the user.
L - load
Download a standard Intel-format file into ram. Then use the G command to execute it.
M - move memory
Move a block of RAM. The user specifies starting, ending and new starting addresses.
O - output data to port
The data byte supplied by the user is sent to an output port also specified by the user.
R - display registers
Display all processor registers and flags.
S - stop processor
Executes HLT instruction. 8088 signals during a halt state may then be examined.
T - test analog i/o
Tests both converters in the analog section. The user may select a sine wave generator (to test the DAC) or an analog echo (which reads ADC data and echo's it to the DAC).
X - examine memory
Memory beginning at an address specified by the user is
displayed on an address by address basis. Each new location may be changed
(by entering new data) or skipped over (by hitting the spacebar). A carriage
return all by itself as input will terminate the command.
A Sample Session on the 8088 SBMCS
This section shows how a few of the monitor commands may be used to put the following program into memory and execute a few times with supplied data to see if it works correctly.
Consider the following program:
1000 03 D8 add bx,ax
1002 03 D1 add dx,cx
1004 CD 95 int 95h
*To load it into memory by hand:
*The <sp> skips over the data in location 1004 (which is already correct) and
the <cr> terminates the command.
*Check the program in memory:
>d 1000 1005
1000 03 D8 03 D1 CD 95
*Load some registers with initial data to be passed to the program:
AX - FF20?1111
BX - 7E36?2222
CX - 3352?3333
DX - A5E8?4444
*Check the register contents:
AX:1111 BX:2222 CX:3333 DX:4444
*Execute the program:
AX:1111 BX:3333 CX:3333 DX:7777
Re-entry by external program at [0000:1004]
*Notice how bx=bx+ax and dx=dx+cx?
*Place a breakpoint at the beginning of the second instruction:
*Check the user code again:
>d 1000 1005
1000 03 D8 CC D1 CD 95
*The 'CC' opcode is the breakpoint interrupt. The user code '03' is now saved in system RAM, to be replaced after the breakpoint is encountered during execution.
*Execute the program again:
AX:1111 BX:4444 CX:3333 DX:7777
Breakpoint encountered at [0000:1002]
*Check the user code again:
>d 1000 1005
1000 03 D8 03 D1 CD 95
*Everything back to normal.…