Technologies:
     RAM (Read/Write)
          Static (flip-flops)
          Dynamic (capacitance of a MOSFET, must be refreshed)
     ROM (Read only)
          PROM (programmable -- one time with PROM burner)
               EPROM (Erasable PROM -- done with UV, whole EPROM erased)
                    EEPROM (Electrically Erasable PROM -- selective locations, but slow)
                         Flash (very fast)

An 8 x 4 PROM

A 4 x 3 Static RAM Memory (Linear Select organization -- 1-D)

2-D organization (to reduce transistro count of decoders)
     Address bus divided into rows and columns (row decoder, column decoder)
     Coincident select

2-D Memory Organization                                                                                                           Single 2-D Static RAM cell

Word organized 2-D RAMs

A 64 x 4 Word-organized 2-D RAM
 

Interfacing with the Microprocessor Module

Example 1: How do we connect a 1K x 8 PROM to a microprocessor with a 12-bit address bus and an 8-bit data bus?
PROM has an active low chip select (CS*) input that, when active reads from the selected address

PROM has 1K = 2^10 = 4x2^8 = 0x400 locations
Microprocessor can access 2^12 = 4096 = 0x1000 locations
Connect MP address lines A9-A0 to PROM's A9-A0 pins
and MEMR* to PROM's CS*
But what do we do with MP's A11 and A10 address lines?
1. Do not connect to MP

     ==> PROM chip will be selected regardless of state (1 or 0) of MP's A11 and A10 lines
     So addresses  00  00 0000 0000 - 00  11 1111 1111 (0x000-0x3FF)
                           01  00 0000 0000 - 01  11 1111 1111 (0x400-0x7FF)
                           10  00 0000 0000 - 10  11 1111 1111 (0x800-0xBFF)
                           11  00 0000 0000 - 11  11 1111 1111 (0xC00-0xFFF)
     all select the same PROM chip
     i.e., the chip is mapped to four different sections of memory (non-unique or incomplete decoding)
     The instructions:
       mov AL,[001]
       mov AL,[401]
       mov AL,[801]
       mov AL,[C01]
     all read the same physical location
     This may or may not be OK!
     Each physical address within the memory chip coresponds to four different logical locations in the MP's address space.
     Extra banks called "shadows" or "ghosts"

2. Getting rid of shadows:
Must decode the high-order MP address lines
For complete decoding, use four of the PROM chips and four three-input NAND gates

 

Programmable NAND Gate Decoding
For decoding a large number of address lines a comparator (programmable NAND) can be used
     E.g. the 74LS677
          It's a 16-input programmable NAND gate
          G* = 0 ==> enabled
          P inputs determine number of NAND inputs that will be inverted
               If P = n, then address inputs A1 through An are inverted

The 74LS677 Comparator
 

Example 2:
Map a 16K x 8 RAM chip to an 8088-based system, beginning at address 0xB8000 using a 74LS677
     16K = 2^4 * 2^10 = 2^14 ==> 14 address lines decoded on chip
     8088 has 20 address lines, so the top 6 will have to be decoded externally.
     0xB8000 = 1011 1000 0000 0000 0000
     Top 6 must be 101110 (A19=1, A18=0, A17=1, A16=1, A15=1, A14=0)
     Two zeroes ==> two 74LS677 address will be inverted (A18 and A14)
     Connect as follows:

Example 3 (original PC):
Interface an Intel 8088 MP with:
     a 1K ROM chip mapped to the top of memory
     a 16K Video RAM chip mapped to block beginning at 0xB0000
     2 64K RAM chips in consecutive banks starting at 0x00000

8088 Address bus, 20 lines ==> 0000 0000 0000 0000 0000
                                              to 1111 1111 1111 1111 1111

1K PROM at top of memory: 1*2^10 ==>   1111 1111 11   00 0000 0000 0000
                                                                to  1111 1111 11   11 1111 1111 1111
i.e., FFC00 to FFFFF                                 off-chip decode     on-chip decode

16K VRAM at B0000: 16*2^10 = 1^14 => 1011 00     00 0000 0000 0000
                                                                to   1011 00    11 1111 1111 1111
i.e., B0000 to B3FFF                                     off-chip      on-chip decode

2 64K RAMs at 00000: 64*2^10 = 2^16 => 0000    0000 0000 0000 0000   RAM-0
                                                                to    0000   1111 1111 1111 1111
i.e.  00000 to 0FFFF                                    off-chip    on-chip decode
                                                                       0001   0000 0000 0000 0000   RAM-1
                                                                to    0001   1111 1111 1111 1111
i.e., 10000 to 1FFFF

Smallest memory needs 10 lines decoded (the PROM)
So we need a 10-input decoder (1024 outputs):

 

The address decoder circuitry:

But 10-to-1024 decoders are not readily available, so why not use a PROM memory to do the same thing?
     There are 4 memory chips and the number of "decoder" output bits is 1024
     Each PROM location would hold a 4-bit word with the bit patterns for the select lines to the four memory chips
          Bit-0 = ROM_SEL*
          Bit-1 = VRAM_SEL*
          Bit-2 = RAM1_SEL*
          Bit-3 = RAM0_SEL*
     The circuit:

The PROM would be programmed as follows:

     PROM decoder        Contents
     addresses                  D3  D2  D1  D0
     0 - 63                         0     1     1     1     To select RAM0
     64 - 127                     1     0     0     0     To select RAM1
     128 - 703                   1     1     1     1     To select nothing
     704 - 719                   1     1     0     1     To select VRAM
     720 - 1022                 1     1     1     1     To select nothing
     1023                           1     1     1     0     To select PROM

But only 64 + 64 + 16 + 1 of the PROM decoder addresses are really used

Better to use a PLA
 

Memory Timing

To interface with memory, we must also look at timing considerations
     Is the memory chip fast enough for a given MP operating at a given clock rate?
     If not, must get faster (more expensive) memory chip
     or insert wait states

Memory read timing parameters (chip manufacturer povides these in spec sheets):
     1. Memory Address Access time (tAA):
          Minimum time from valid address in to valid data out of memory chip
               (measures performance of on-chip address decoders)
     2. Memory Read Access time (tRD):
          Minimum time from active RD* to valid data

Microprocessor Mem Read cycle times (depend on clock rate):
     1. Address Valid to Data Valid (tAVDV)--
          MP latches data after that time
          It's the time memory has after address is valid
          Doesn't inlcude buffer delays
     2.  Read Low to Data Valid (tRLDV)--
Other MP Mem Read timing parameters (see following diagram):
     Clock Low to Clock Low (tCLCL) = 200 ns for a 5 MHz 8086
     Clock Low to Address Valid (tCLAV) = 110 ns for 5 MHz 8086
     Data Valid to Clock Low (tDVCL) = 30 ns for 5 MHz 8086
     Clock Low to Read Low (tCLRL) = 35 ns for 5 MHz 8086

Fig. Read timing diagram for the 8086

From diagram: tAVDV = 3*tCLCL - tCLAV - tDVCL = 460 ns for 5 MHz 8086

Memory chip's Address Access time must respond within this timing window
     i.e., tAA must be less than tAVDV

From diagram tRLDV = 2*tCLCL - tCLRL -tDVCL = 335 ns for 5 MHz 8086

Memory chip's Read Access time must also respond within this timing window
     i.e., tRA must be less than tRLDV

There are similar parameters for memory write operations

In addition, buffer delays must also be taken into account
     For example on a buffered miminum mode 8086 system,
     total propagation delay (buffers + memory) must be less than tAVDV

t(Buffer delays) + tAA(memory) < tAVDV (8086)
Here: 30 + 40 + tAA(memory) + 30 < 460 (for 5 MHz like the above)
     tAA(memory < 360 ns