Intel 8086/8088 Microprocessor
   (Similar in many ways to core CPU of many microcontrollers -- e.g. 8051)

Two processors in one:
     Execution unit (EU)
     Bus interface unit (BIU)
     Form a two-stage pipeline
     New instruction place in prefetch queue

Fig. 1. 8086 functional block diagram

BIU functional parts:
     Prefetch queue
     Register Array
     Internal data bus
     BIU control unit
EU functional parts:
     Array of general processing registers
     ALU and flags register
     EU Control unit

Microprocessor Timing
Instruction cycle composed of:
    Bus (machine) cycles composed of:
Common (standard) types of bus sycles:
     MEMR*, MEMW*, IOR*, IOW*

Fig. 2. Simplified bus cycle timing diagram
     This what standard memory-I/O devices expect

16 bit data bus, 20-bit address bus
     16 data, 20 address, 17 control/timing, 3 power = 56
     But 8086 has just 40 pins
     16 Address/Data lines are multiplexed (AD0-AD15)
          Also A16-A19 with S3-S6

8086 Pinouts (min mode)
MN/MX* (in): Minimum/maximum operating mode
AD0-AD15 (out): multiplexed address/data bus signals
A16/S3-A19/S6 (out): Address/status
     S4-S3: 00-ES, 01-SS, 10-CS, 11-DS
     S5: INTE flag, S6=0
BHE* (out): Bus High Enable - determines if byte or word memory access (with A0)
NMI & INTR (in): interrupt request inputs
INTA* (out): Interrupt acknowledge
CLK (in): System clock
RD* (out): Read bus cycle in progress
WR* (out): Write bus cycle in progress
M/IO* (out): memory or I/O transfer occuring over bus
DT/R* (out): Data transmit/receive (direction of data transfer through external buffers)
DEN* (out): Data enable, signals that bus lines are being used to transfer data
HOLD (in): Causes 8086 to relinquish bus, used in DMA
HLDA (out): Hold acknowledge, signals bus lines have been relinquished
TEST* (in): If high, 8086 enters idle mode (for use with other processors, e.g., 8087)
READY (in): To generate wait states (for slow memory/I/O devices)
RESET(in): Reset processor, terminate current activity, initialize registers

Fig. 3. 8086 pinouts

Fig 4. Real bus cycle 8086 timing diagram

Generating "standard" control signals (MEMR*, MEMW*, IOR*, IOW*)

Demultiplexing the bus
     Must latch in Address signals
          Use falling edge of ALE

Clock and Reset requirements
     2-12 MHz, 33% duty cycle, low: -.5 to 0.t volts, high 3.9-5.0 volts
     Reset state: CS=0xFFFF, SS=DS=ES=IP=Flags=0
          RESET must be held high for at least 4 clocks
          and must be synchronized with system clock
          and must be activated in synchronization with falling clock of a new T state
     Use Intel 8284 Clock Generator to do both

Building the CPU module: The 8284 Clock Generator
CLK part:
          from a piezoelectric crystal oscillator (between X1 & X2 inputs)
          or from frequency generator (EFI input)
          F/C* determines which
          Buffered clock signal with required characteristics
          fclock = 1/3 finput
RESET part:
     8284 generates properly-synched RESET whenever RES* goes low
     User wants a system reset when:
          reset button is pressed
          or power first applied
      Need to hold RES* low as voltage builds up to +5 Volts
          Attach capacitor to ground --> RC time delay when power applied
               Also RES* will be held low while capacitor is charging
               (See in-class circuit)
READY part:
      8284 provides synched READY signal
      Slow device may request wait state at any time
      But for 8086 to generate the extra T3 state, READY must be pulled low just before start of T3
      8254 generates READY at this time after RDY1 or RDY2 inputs are pulled low

Building the CPU Module: Interfacing with the busses
8086 can't be connected directly to memory and I/O devices
Interface circuits are needed because:
     1. Limited driving capacity of the microprocessor
          Ioh - output high level drive current -- max current A/D lines can provide when high (400 uA for 8086)
               TTL devices sink 40 uA from a high input (CMOS much less)
                    So when high an 8086 pin can drive only up to 400/40 = 10 TTL devices
          Iol - output low level sink current -- max current A/D lines can sink when low (2.5 mA for 8086)
               TTL devices source 1.5 mA to a low input
                    So when low an 8086 pin can drive only 2.5/1.6 = 1 TTL device
     2. Need to isolate signal paths
          Only one circuit should drive buses at a time
          When CPU is driving the bus lines, other circuits must not (Bus Contention)
               Interface must provide a way of avoiding this
     3. Address/Data demultiplexing
           Interface must separate address and data signals from the 8086
           and make sure the address values are on the bus during the entire bus cycle
     4. Make sure the data flows in the correct direction
     A. Tristate buffers (e.g., 74LS244 octal buffer):
          Vout = Vin only when Enable signal is active
          Otherwise output disconnected from input (high impedence state)
          Also provide increased source/sink current capacity
               Ioh drive capacity = 3mA, So can drive 3000/40 = 75 TTL loads in high state
               Iol = 12mA, So can drive 12/1.6 = 7.5 TTL loads in low state
          Unidirectional ==> good only for control signals
     B. Transcievers (e.g., Intel 8286 or 74LS245 octal trancievers)
               For buffering bidirectional bus lines (e.g. data lines)
               Two tristate buffers in parallel
               Use 8086 DEN* and DT/R* signals to enable in the correct direction
               See Figure
               Increased source/sink current:
                    Iol = 32mA, so 32/1.6 = 20 TTL loads
                    Ioh = 5 mA, so 5000/40 = 125 TTL loads
     C. Transparent latches (e.g., Intel 8282 or 74LS373 octal latch)
          Can demux the bus -- i.e., create address bus
          While STB is high, Q output = D input (data passed through)
          STB makes hi-to-low transition latches D input
               Use ALE from 8086 as STB signal
          Also provides current drive capability
               Iol = 32 mA ==> 125 TTL loads
               Ioh = 5 mA ==> 20 TTL loads
          See figure
          Note Data lines are NOT demuxed
               OK since there's never data on the A/D lines until after address signals are gone
               i.e., Mem and I/O don't access data lines until T3 when address info is gone

Figure 5. A complete Minimum mode 8086 CPU module

8086 Memory organization
8086 permits both word and byte access
Logical memory byte address space (0-0xFFFFF)
     A19-A1 select a byte in either bank
     Maps to an even bank (D7-D0) and an odd bank (D15-D8)
     Even bank chip selected by A0
     Odd band chip selected by BHE*
          A0=0 selects even bank ==> even byte accesses (data on D7-D0)
          BHE*=0 selects odd bank ==> odd byte access (data on D15-D8)
          Both low selects both banks ==> word access (data on D15-D0)
       Instruction       Logical Address   A19-A1   A0  BHE*  Within bank address
       mov al,[0]           0                       00...00      0      1        0 in even bank
       mov al,[1]           1                       00...00      1      0        0 in odd bank
       mov al,[2]           2                       00...01      0      1        1 in even bank
       mov al,[3]           3                       00...01      1      0        1 in odd bank
       mov ax,[0]          0                       00...00      0      0        0 in both banks
       mov ax,[2]          2                       00...01      0      0        1 in both banks
       mov ax,[3]  TWO BUS CYCLES REQUIRED:
                 1st cycle   3                       00...01      1      0        1 in odd bank
                 2nd cycle  4                       00...10       0      1        2 in even bank

8086 Microprocessor in Maximum mode
For systems with more than one processor (multiprocessor systems)
     Processors can execute concurrently
          Increased performance
     Can have special-purpose processors (e.g., numeric coprocessor, I/O processor)
     Some issues:
          Resource sharing
          Bus contention
     But processors synchronize activities
     Communicate with each other (IPC)
     Share resources with each other
     Avoid interference (bus contention) with each other
          So there must be more control signals in Max mode
               RQ*/RT*: Bus request / grant
               LOCK*: To prevent one processor from accessing busses while other is
               QS0,QS1: Queue status
               Standard control signals are encoded into 3 status signals (S0*,S1*,S2*)
                   These need to be decoded
                   Intel 8288 Bus controller performs this task

Intel 8088 Microprocessor (used in original PC)
Difference in BIU
     8-bit data bus
         So no even/odd memory addresses
         No BHE* signal
     4-bit-deep prefetch queue

Fig. 6. 8088 block diagram

Fig 7 (6-26). 8088 Pinouts

8088 Pinout differences:
     AD15-AD8 become A15-A8
     M/IO* becomes IO/M*
     BHE* replaced by SS0* (status signal, used with DT/R* and IO/M*)

Several memory and I/O chips designed to interface directly with the 8088
     8185: 1024-byte static RAM
     8755: 2048-byte EPROM with 2 I/O ports
     8155: 256x8 static RAM, two 8-bit ports, one 6-bit port, timer
Could be used to design a 4-chip complete microcomputer system

Fig. 8. 4-bit 8088-based microcomputer system

Modern Microprocessors (Pentium)
32-bit Address bus (4 Gbytes)
64-bit Data bus
BHE1*-BHE7* used to select memory banks & amount of data transferred

Fig. 9. Pentium pinouts

Fig.10. Pentium memory banks