1st Workshop on Architectural Reliability (WAR-1)

Sunday, November 13, 2005

to be held in conjunction with

38th International Symposium on Microarchitecture (MICRO-38)

Barcelona, Spain

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ADVANCE PROGRAM

2:00 - 2:30 Restore: Symptom Based Soft Error Detection in Microprocessors
Nicholas J. Wang, Sanjay J. Patel
University of Illinois at Urbana-Champaign
2:30 - 3:00 Error Detection and Recovery in High Performance Microprocessors prone to High Transient Error Rates
Aneesh Aggarwal
Binghamton University
3:00 - 3:30 A Microarchitectural Analysis of Soft Error Propagation in a Production-Level Embedded Microprocessor
Jason Blome, Scott Mahlke, Daryl Bradley, Kristzian Flautner
University of Michigan / ARM
3:30 - 4:00 COFFEE BREAK
4:00 - 4:30 Reliability Requirements of Control, Address, and Data Operations in Error-Tolerant Applications
Darshan D. Thaker, Diana Franklin, Venkatesh Akella, Frederic T. Chong
University of California - Davis / California Polytechnic University / University of California - Santa Barbara
4:30 - 5:00 Assessing SEU Vulnerability via Circuit-Level Timing Analysis
Kypros Constantinides, Stephen Plaza, Jason Blome, Bin Zhang, Valeria Bertacco, Scott Mahlke, Todd Austin, Michael Orshansky
University of Michigan / University of Texas at Austin
5:00 - 5:30 Reliability Tradeoffs in Design of Cache Memories
Hossein Asadi, Vilas Sridharan, Mehdi B. Tahoori, David Kaeli
Northeastern University

last updated on : Friday, 04 November 2005 08:37 PM +0100 (Barcelona time)