Networking and Parallel Processing Lab.
Mobile Ad hoc Networking Protocols
Summary: Mobile Ad hoc networks (MANETs) are infrastructureless networks of mobile devices connected using wireless communication. They have several important military and commercial applications and are forecast to become even more important in the future. In practice, and in simulation, these networks do not perform well (much below expected capacity). They also suffer from unfairness unreliability and unexpected behavior. This is due to a number of reasons at different levels of the networking protocol stack. Our research in this area focuses on solving some of these issues.
Application Level Protocols for Sensor Networks
Summary: There are a number of proposed protocols for routing, medium access and data aggregation for sensor networks . optimizing the process of transporting a predefined reporting discipline to an observer. In contrast, little work has addressed the problem of which data to send and when to send it . how to determine the appropriate reporting discipline. An inefficient reporting discipline can result in bad performance both from an application perspective as well as from a networking and energy efficiency perspective, even if aggregation is carried out. For example, an inefficient reporting discipline may result in data being sent at too high a rate (or too low a rate), from sensors that are not in areas of interest, or redundantly from sensors reporting on the same phenomenon. In addition, congestion may arise if the reporting discipline is not carefully selected and monitored. Developing application protocols that converge on an efficient reporting discipline is the focus of our research. Ideally, the application protocol will allow an observer to specify her interests in terms of the phenomena, independent of the underlying sensor network infrastructure. The protocol will then converge on a reporting discipline that achieves the desired application objectives while minimizing the load on the network.
Our approach to achieving this objective is an application level framework that works as follows. An interest expressed in terms of the phenomenon is diffused through the network, setting up a reduction tree from the sensors towards the observer. The sensors report through this tree and intermediate nodes serve as aggregation and control points that configure the subtree rooted at them. The sensors respond with their coverage capabilities relative to the diffused interest query. The observer then selects a subset of the available coverage to meet its interest, and informs the responsible sensors to set up the reporting discipline. Note that the observer informs only its directly connected children, which in turn select the coverage from their own children to meet their responsibility to the observer. This operation is carried out recursively . all aspects of protocol operation are localized. In addition to the application requirements, the reporting discipline must be effective from a networking perspective . it should not create congestion and it should rotate responsibilities to balance the load. Finally, the protocol should adapt the reporting discipline in response to network and phenomenon dynamics. There are several open research problems that exist in such a framework . we are currently pursuing solutions to them.
Faris is maintaining a conference list page for mobile networks. Please contact him to add a conference or to add your name to the working list on any conference.
Computer simulation has become accepted as the third method for scientific experiments (mathematical modeling and experimental measurements being the other two). Simulation provides well known advantages over the other two methods and is a primary research vehicle in many diciplines. As the size of the problems continues to grow, there is considerable interest in building simulation engines capable of simulation of complex systems. Parallel simulation is a promising approach to scale the size and performance of large scale system simulation. With parallel simulation, one of the primary challenges is synchronization among the simulator processes to exchange events that cross the process boundary. We focus on optimistically synchronized simulators where the simulators process local events without coordination with other simulators. In such an environment, a process may erroneously advance its time because an event from another process has not been received yet. To recover from such events, the processes take checkpoints of their state. If a process receives an event in its past, it rolls back to the closest checkpoint before the event and resumes the computation from there. Our research focuses on optimization of several aspects of the simulator engine.
Current Research Problems include:
High Performance Computer Architecture (Processing in memory, parallel processing, polymorphic computing)
As we continue to head towards deep submicron VLSI fabrication processes, many of the accepted principles governing computer architecture design are changing. This change is also fueled by the changing nature of workloads that are becoming increasingly heavy in multimedia content (with intensive memory requirements and a large degree of inherent parallelism). Wire delays will dominate gate delays, and a distributed modularized design where most communication is localized becomes necessary. Also, techniques for low-power design are important, especially for mobile devices (which will also account for an increasing segment of the market). Revolutionary architectural models are needed to address these trends. For example, processor speed has increased at a much faster yearly rate (60%) than that of DRAM memory speed (7%), causing a wide and increasing gap between the memory needs of CPUs and the bandwidth that the memory subsystem is able to deliver. Large and expensive caches take up over 50% of the die area of modern CPUs, but cannot hide the memory bottleneck successfully, especially for data intensive applications. Integrating processing logic with memory is a promising approach for alleviating this problem because: (i) DRAM is much denser than SRAM (50X factor in some recent designs); (ii) the bandwidth exposed to the processor is on the order of terabytes per second (bandwidth at sense amplifiers), vs the few hundred MBytes per second available on current generation of system buses; and (iii) the latency for memory access is smaller (since data only has to travel within chip).
Current Research Problems include: