Abstract: Shared-Control: A Paradigm for Supporting Control Parallelism on SIMD-like Architectures.

Parallel architectures are commonly classified according to their control organization as either MIMD or SIMD. MIMD machines have a distributed control organization, with every PE having a control unit capable of sequencing an independent computation. In contrast, SIMD machines have a centralized control organization, where the PEs share a control stream broadcast by a single control unit. This organization makes the PEs simple and regular because: (1) the control hardware is shared, and (2) the operation is synchronous -- no hardware is required for synchronization and conflict resolution. Unfortunately, the SIMD model has a number of disadvantages that have caused it to be viewed as a special purpose, and even obsolete, model for general purpose parallel computation. Chief among these disadvantages is the inflexible control organization. More precisely, control parallelism cannot be supported without time-sharing the use of the control unit among the different required control paths -- executing them sequentially.

This dissertation develops and investiages a new model for constructing centralized control architectures. This model, called shared control, overcomes the inefficiency of SIMD machines on control parallel applications by sharing the control organization at a fundamentally different level -- the instruction (or function) level. Thus, all the PEs executing the same instruction, but not necessarily the same control thread, receive their control from the same control unit concurrently. Thus, the performance of the system is decoupled from the control nature of the application, and is bound to that of the control flow graph (CFG) of the instruction set architecture (ISA). Since this CFG is static, scalable performance independent of the control nature of the application is obtained using a centralized control organization.

Under shared control, the control organization can be viewed as a shared microprogrammed control unit. Sharing this control unit at the instruction level necessitates the support of all the instructions in the ISA concurrently. This makes the design of the shared microcode a fundamentally different problem than the design of traditional, non-shared microcode. The criteria for optimizing the shared microcode is developed and optimizations to the shared control organization are investigated. The utility of shared-control is studied through the design and simulation of a massively parallel shared-control architecture.

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