Abstract: Composing Functional Unit Blocks for Efficient Interpretation of MIMD Code Sequences on SIMD Processors.

The branching regions of data-parallel programs can lead to serial execution on a SIMD processor. However, recent investigations show that these branching regions can be compiled into instruction sequences that are placed in the Processing Element (PE) memories for interpretation. Thus, when the branching region is reached, the control unit of the SIMD processor executes an instruction interpreter that causes the concurrent execution (through interpretation) of the branching code at each PE. Interpretation incurs some overhead and therefore, it is necessary to carefully design the instruction set to be interpreted. In this paper, we present a software architecture called Compose with 9 functional units and show that these functional units can be composed together to realize (at least) 42 distinct useful instructions. Thus, each iteration of the interpreter loop pays only the overhead of broadcasting execution orders for a few operations and yet manages to interpret (in parallel) a much larger set of operations.
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