Store Conditional Bug

From Msim

Revision as of 21:19, 21 July 2009 by Jloew (Talk | contribs)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search

This page refers to a mishandling of Store Conditional instructions which missed dealing with their physical register requirements.

The Problem

Since Store Conditional instructions require a physical register, the physical register must be written too, committed to architectural state and given ready times. Stores do not normally do this since they generally do not have physical registers.


At selection, when a store is written into the LSQ we must check if a physical register exists and handle it. See bolded code:
               if(rs->in_LSQ && ((MD_OP_FLAGS(rs->op) & (F_MEM|F_STORE)) == (F_MEM|F_STORE)))
                       //stores complete in effectively zero time, result is written into the load/store queue, the actual store into
                       //the memory system occurs when the instruction is retired (see commit())
                       //This acts as if there is no write buffer
                       rs->issued = TRUE;
                       rs->completed = TRUE;

                       //If the store has a physical register (Store Conditional), make the register as written to.
                       //This is too early, but isn't checked until commit (when it would be ok anyway).
                       if(rs->physreg >= 0)
                               //Set ready times
                               cores[core_num].reg_file.reg_file_access(rs->physreg,rs->dest_format).spec_ready = sim_cycle + rs->exec_lat;
                               cores[core_num].reg_file.reg_file_access(rs->physreg,rs->dest_format).ready = sim_cycle + rs->exec_lat + cores[core_num].ISSUE_EXEC_DELAY;

                               cores[core_num].reg_file.reg_file_access(rs->physreg,rs->dest_format).state = REG_WB;

                               std::cerr << "mispredicted store" << std::endl;
Personal tools