A Core represents a single processor that exists on some chip. For all intents and purposes, it has no reliance on other cores to function - it is self-sufficient. Within M-sim, Cores share the L3 cache as use the L3 cache as the memory gateway to the simulated off-chip memory.
Left off at Line 78 in cmp.h
Core is essentially an abstraction of a processor designed in a fashion such that multiples can exist and can communicate with each other and the simulation machine environment.
Prior versions of M-sim had 1 Core and ran threads on it. Now, multiple cores can be run, and are independent of each other (unless the L3 cache is enabled).
core_t is designed as follows
- unsigned int mem_access_latency(int blk_sz): Acquires the latency of an access to main memory of size blk_sz
- std::vector<int> (*fetcher)(unsigned int): Function pointer to the fetching scheme used by the core
- unsigned int id: Unique identifer for the core
- unsigned int max_contexts: Maximum number of threads supported by the core (SMT on CMP)
- processor_power power: Wattch implementation object
- std::vector<context *> contexts: The threads that exist on the core
- std::vector<int> context_ids: The ids for the threads that exist on the core (FIXME: This is not needed but still in use)
- cache_t *: cache_dl1, cache_dl2, cache_il1, cache_il2, dtlb, itlb: The caches on the core (Level 1, Level 2 and TLBs) (Data or Instruction caches)
- int cache_dl1_lat, cache_dl2_lat, cache_il1_lat, cache_il2_lat, tlb_miss_lat: Latencies for the caches and the TLB (dtlb and itlb share same latency).
- std::vector<bpred_t *> pred: The branch predictors on the core
- std::vector<int> pred_list: Specifies which context owns the nth branch predictor
- std::vector<bpred_t *> load_lat_pred: The load hit predictors on the core
- std::vector<int> load_lat_pred_list: Specifies which context owns the nth load hit predictor
- std::vector<int> ROB: The sizes of the ROBs on the core
- std::vector<int> ROB_list: Specifies which context owns the nth ROB
- std::vector<int> LSQ: The sizes of the LSQs on the core
- std::vector<int> LSQ_list: Specifies which context owns the nth LSQ
- std::vector<int> IFQ: The sizes of the IFQs on the core
- std::vector<int> IFQ_list: Specifies which context owns the nth IFQ
- reg_file_t reg_file: The integer and floating-point physical register file
- inflight_queue_t<RS_link,seq_sort> ready_queue: A ready queue abstraction. This handles instructions that have been declared as ready (pointed to using RS_link). seq_sort refers to sorting these instructions by program order. Instructions leave this queue in program order for execution.
- inflight_queue_t<RS_link> event_queue: Handles signaling the completion of the writeback of an instruction. Instructions leave this queue in order of earliest to complete writeback.
- inflight_queue_t<RS_link> waiting_queue: A waiting queue abstraction. Instructions that are not yet ready for execution are here.
- inflight_queue_t<RS_link> issue_exec_queue: Handles signaling the completion of the execution of an instruction. Instructions leave this queue in order of earlier to complete execution.
- issue_queue_t iq: The issue queue.
- smt.h: Required to use contexts
- iq.h: Required to use the issue queue
- power.h: Required for power modeling
- inflightq.h: Required for modeling of inflight instructions (ready, waiting, issue_exec and event queues)