Changelog

From Msim

Revision as of 20:21, 13 July 2009 by Jloew (Talk | contribs)
Jump to: navigation, search

This page details changes since the relase of Version 3.0 of M-sim. Information about the changes is provided in case mistakes were made and to provide greater understanding of the simulator.

Contents

Upcoming

A file handler class for both debugging as well as creating accurate and portable checkpoints.
Syscalls OSF_SYS_getgroups and OSF_SYS_mkdir are now supported.
Conditional Memory support is being added.
Issue_Inorder has been fixed.
Libexo is being removed from the simulator.
regs_t now supports input operator for replacing libexo (regs.[hc]).
mem_t now supports input operator for replacing libexo (memory.[hc]).
Tagset error has been corrected.

June 16th 2009

Machine.def updates (RPCC, STQ_C, STL_C, Comments).
Loader issues related to gcc 4.3.2 support.
Rollback support for mt_fpcr (sim-outorder.c)
Rollback support for STQ_C and STL_C (sim-outorder.c)
F_TRAPs should (and have, but apparently this was lost) cause the ROB to drain before rename (sim-outorder.c)
Rollback can't rollback over a F_TRAP (see above, cmp.c, cmp.c)
regs_t now supports output operator (input pending) for replacing libexo (regs.[hc]).
mem_t now supports output operator (input pending) for replacing libexo (memory.[hc]).
Added minor setsysinfo and getsysinfo support (syscall.c).
Added support for fstat64 (syscall.c).
Added support for exit_group (syscall.c).
Fixed obreak (syscall.c).
Fixed uname, which also provides utsname (syscall.c).
Corrected incorrect == instead of != in mmap. Improved overall behavior but still not full support (syscall.c).

May 12th 2009

Write Buffer emergency patch issued. Could get caught in an infinite loop trying to remove elements from an empty write buffer.

May 5th 2009

Cache fixes made. Correction made to the usage of bus_free. A write buffer (from processor to first level cache) is now implemented per core - this resolves the bzip2 and gzip problem without having to use the "read data block" hack.

April 24th 2009

Main.c now properly includes fstream (#include<fstream>).

April 20th 2009

Num_Cores not being handled correctly through a config file has been fixed. Also, MAX_LINE_ARGS in options.c has been increased to handle the large number of options required for CMP.

April 4th 2009

Options.c is updated to handle newly created config files from dumpconfig. Minor code adjustment.
Dram bug with accesses across two banks is fixed, other minor tweaks.
Cache access has been updated to return an unsigned long long, BOUND_POS is no longer needed.
Inflight Queues have been altered to no longer assume compiler eliding, this required const enforcing in the rob.h as well.
Issue Queue has been altered to no longer assume compiler eliding.
Optimizations done in sim-outorder.c.

March 6th 2009

Added -max:cycles support - would be nice to avoid the check each cycle though.
Dram modeling support is now available - the default is the old chunk style method.
Memory bus width is now 4 bytes by default.

February 12th 2009

mem_access_latency (defined in cmp.h) now takes 4 parameters (address, size, when, context_id) compared to just size. This is intended for DRAM access modeling. This affects cmp.c, cmp.h and sim-outorder.c
OSF_SYS_write is removed from machine.h and replaced in syscall.c
Optimization: When checking the LSQ for a store forward, the for loop was not used effectively.

January 24th 2009

Trivial: Removed commented out lines from main.c
Trivial: Re-enabled fclose(outfile) in context desructor in smt.c - fixes ~1K mem leak
Bug 1: Fixed "issued inst not spec ready" for floating point insts (actually affected all, but only mattered in floating point cases)
Bug 2: Commit now looks at the correct list of remaining contexts.

Personal tools