Changelog

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=== Upcoming ===
=== Upcoming ===
 +
mem_bus_width default value is changing from 8 to 4 bytes.<br>
 +
A dram class which can be inherited from to provide main memory modeling - a simplified version will be included in the release.<br>
 +
A file handler class for both debugging as well as creating accurate and portable checkpoints.<br>

Revision as of 21:20, 19 February 2009

This page details changes since the relase of Version 3.0 of M-sim. Information about the changes is provided in case mistakes were made and to provide greater understanding of the simulator.

Upcoming

mem_bus_width default value is changing from 8 to 4 bytes.
A dram class which can be inherited from to provide main memory modeling - a simplified version will be included in the release.
A file handler class for both debugging as well as creating accurate and portable checkpoints.


February 12th 2009

mem_access_latency (defined in cmp.h) now takes 4 parameters (address, size, when, context_id) compared to just size. This is intended for DRAM access modeling. This affects cmp.c, cmp.h and sim-outorder.c
OSF_SYS_write is removed from machine.h and replaced in syscall.c
Optimization: When checking the LSQ for a store forward, the for loop was not used effectively.

January 24th 2009

Trivial: Removed commented out lines from main.c
Trivial: Re-enabled fclose(outfile) in context desructor in smt.c - fixes ~1K mem leak
Bug 1: Fixed "issued inst not spec ready" for floating point insts (actually affected all, but only mattered in floating point cases)
Bug 2: Commit now looks at the correct list of remaining contexts.

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