Default Configuration

From Msim

Jump to: navigation, search
Command Line Parameter Type Default Value Description
-config string <null> This is used to load a configuration file into the simulator
-dumpconfig string <null> This saves the current configuration of the simulator into a file
-h true/false false print help message
-v true/false false verbose operation
-d true/false false enable debug message
-i true/false false start in Dlite debugger
-seed int 1 random number generator seed (0 for timer seed)
-q true/false false initialize and terminate immediately
-redir:sim string <null> redirect simulator output to file (non-interactive only)
-redir:prog string <null> redirect simulated program output to file (all benchmarks)
-redir:err string <null> redirect simulated program output (stderr) to file (all benchmarks)
-nice int 0 simulator scheduling priority
-max:inst long long 1000000 maximum number of inst's to execute
-max:cycles long long -1 maximum number of cycles to execute
-fastfwd long long 1000000 number of insts skipped before timing starts
-ptrace set of strings <null> generate pipetrace, i.e., <fname or stdout or stderr> <range>
-pcstat set of strings <null> profile stat(s) against text addr's (mult uses ok)
-power:print_stats true/false true print power statistics collected by wattch?
-num_cores unsigned int 1 Number of processor cores
-max_contexts_per_core int -1 Number of contexts allowed per core (-1 == limit is number of contexts, 0 is invalid)
-fetch:speed int 1 speed of front-end of machine relative to execution core
-decode:width unsigned int 4 instruction decode B/W (insts/cycle)
-issue:width unsigned int 4 instruction issue B/W (insts/cycle)
-issue:inorder true/false false run pipeline with in-order issue
-issue:wrongpath true/false true issue instructions down wrong execution paths
-commit:width unsigned int 4 instruction commit B/W (insts/cycle)
-iq:issue_exec_delay int 1 minimum cycles between issue and execution
-fetch_rename_delay int 4 number of cycles between fetch and rename stages
-rename_dispatch_delay int 1 number cycles between rename and dispatch stages
-lsq:size unsigned int 48 load/store queue (LSQ) size
-rob:size unsigned int 128 reorder buffer (ROB) size
-fetch:policy string icount fetch policy, icount, round_robin, dcra
-recovery:model string squash Alpha squash recovery or perfect predition: squash or perfect
-iq:size unsigned int 32 issue queue (IQ) size
-rf:size unsigned int 128 register file (RF) size for each the INT and FP physical register file)
-res:ialu unsigned int 4 total number of integer ALU's available
-res:imult unsigned int 1 total number of integer multiplier/dividers available
-res:memport unsigned int 2 total number of memory system ports available (to CPU)
-res:fpalu unsigned int 4 total number of floating point ALU's available
-res:fpmult unsigned int 1 total number of floating point multiplier/dividers available
-write_buf:size unsigned int 16 write buffer size (for stores to L1, not for writeback)
-cache:dl1 string dl1:256:32:4:l l1 data cache config, i.e., {<config> or none}
-cache:dl1lat int 1 l1 data cache hit latency (in cycles)
-cache:dl2 string ul2:512:128:8:l l2 data cache config, i.e., {<config> or none}
-cache:dl2lat int 10 l2 data cache hit latency (in cycles)
-cache:il1 string il1:512:32:2:l l1 inst cache config, i.e., {<config> or dl1 or dl2 or none}
-cache:il1lat int 1 l1 instruction cache hit latency (in cycles)
-cache:il2 string dl2 l2 instruction cache config, i.e., {<config> or dl2 or none}
-cache:il2lat int 10 l2 instruction cache hit latency (in cycles)
-tlb:itlb string itlb:16:4096:4:l instruction TLB config, i.e., {<config> or none}
-tlb:dtlb string dtlb:32:4096:4:l data TLB config, i.e., {<config> or none}
-tlb:lat int 30 inst/data TLB miss latency (in cycles)
-bpred string bimod branch predictor type {nottaken or taken or perfect or bimod or 2lev or comb}
-bpred:ras int 8 return address stack size (0 for no return stack)
-bpred:spec_update string <null> speculative predictors update in {ID or WB} (default non-spec)
-bpred:bimod int 2048 bimodal predictor config: <table_size>
-bpred:2lev set of ints [ 1 1024 8 0 ] 2-level predictor config (<l1size> <l2size> <hist_size> <xor>)
-bpred:comb int 1024 combining predictor config (<meta_table_size>)
-bpred:btb set of ints [ 512 4 ] BTB config (<num_sets> <associativity>)
-cpred string bimod cache load-latency predictor type {nottaken or taken or perfect or bimod or 2lev orcomb}
-cpred:ras int 0 return address stack size (0 for no return stack)
-cpred:bimod int 2048 cache load-latency bimodal predictor config (<table_size>)
-cpred:2lev set of ints [ 1 1024 8 0 ] cache load-latency 2-level predictor config (<l1size> <l2size> <hist_size> <xor>)
-cpred:comb int 1024 cache load-latency combining predictor config (<meta_table_size>)
-cpred:btb set of ints [ 512 4 ] cache load-latency BTB config (<num_sets> <associativity>)
-mem:config string chunk:4:300:2 Main memory configuration
-cache:dl3 string none l3 data cache config, i.e., {<config> or none}
-cache:dl3lat int 30 l3 data cache hit latency (in cycles)
-cache:il3 string none l3 instruction cache config, i.e., {<config> or dl3 or none}
-cache:il3lat int 30 l3 instruction cache hit latency (in cycles)
Personal tools