Caches: Store Misses

From Msim

Jump to: navigation, search

This page discussions problematic behavior within the cache_access function (cache_t::cache_access).


The Problem

The cache access handlers (except when going to main memory) do not distinguish between loads and stores. This results in stores generating cache misses. Since all misses must be serviced, latency is dependent on both the cache latency as well as the number of pending misses.

Versions Affected

This affects all versions of M-sim as well as simplescalar.


The extent this affects benchmarks is not yet clear. However, running bzip2 or gzip through their initialization phase will cause huge cache latencies to appear. This bug will cause inflated latencies to appear but it may not be sufficient to cause a problem if stores are sparse or there are few accesses to the same set. This does not occur during fast forwarding as latency values generated during fast forwarding as ignored anyway.


See Fetch Issue Delay Problem. The propagation of cmd was technically incorrect.

Personal tools