06-16-09-Machine Def

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This describes the updates made to machine.def to support additional opcodes, refine current support.

RPCC

The prior implementation:

/* FIXME: dumb implementation */                                  \
SET_GPR(RA, ULL(0));

Is replaced with a timer based off of sim_cycle (with PCC_OFF unimplemented and increments of 1).

SET_GPR(RA, sim_cycle & LL(0xffffffff));

STQ_C and STL_C

Both of these instruction now do the following (after storing and fault detection):

 SET_GPR(RA, 1);

A lock_flag is not implemented (and needs to be for any shared memory support). Setting RA (the source data) to 1 afterwards indicates success of the lock - 0 indicates failure and try again which can infinitely loop - see atomic instructions.

Comments

  • ECB comments that we may be able to call a cache_flush variant to implement this
  • FETCH and FETCH_M now indicate that the alpha handbook indicates these are "unlikely to help" and that these are optional anyway
  • STQ_C and STL_C note that we may want to consider this instruction using a physical register
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