04-04-09-Dram

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This refers to the fixes to dram.h and dram.c with the primary fix involving a bus when accessing across two banks.


When generating an access, it could cross into a second bank. The previous code used a continuation flag to handle large accesses and this would be set incorrectly if we accessed a new bank - resulting in a latency error (latency of additional bytes + ready time for the new bank, which was not adjusted for the new access)

Original Code:

unsigned int dram_basic::mem_access_latency(md_addr_t addr, int size, tick_t when, int context_id)
{
 assert((size%bus_width)==0);
 int offset = 0;
 unsigned int latency = 0;
 while(size>0)
 {
  size-=bus_width;
  tick_t doneat = std::max(latency,mem_access_latency_helper(addr+offset,offset!=0,when+to_dram,context_id));
  latency = (doneat - when);
  offset+=bus_width;
 }
 return latency;

New Code: Now, if the bank the bank changes, we do not set the continuation flag. If the bank repeats, we do set the flag.

unsigned int dram_basic::mem_access_latency(md_addr_t addr, int size, tick_t when, int context_id)
{
 assert((size%bus_width)==0);
 int offset = 0;
 unsigned int latency = 0;
 unsigned int target_bank = (unsigned int)-1;
 
 while(size>0)
 {
  size-=bus_width;
  unsigned int cur_bank = ((addr+offset)>>row_bits)%num_banks;
  tick_t doneat = std::max(latency,mem_access_latency_helper(addr+offset,target_bank==cur_bank,when+to_dram,context_id));
  
  latency = (doneat - when);
  offset+=bus_width;
  target_bank = cur_bank;
 }
 return latency;
}



Comment changed in dram.h, forgot bus_width details:
Original:

*              configuration -> <first_chunk_latency>:<next_chunk_latency>

New:

*              configuration -> <bus_width>:<first_chunk_latency>:<next_chunk_latency>

In dram_basic (dram.h), the values within vector banks and vector status should be unsigned ints:
Original:

std::vector<int> banks, status;

New:

std::vector<unsigned int> banks, status;

In the original dram model (dram_default), chunks should be an unsigned int:
Original:

int chunks = (size + (bus_width - 1)) / bus_width;

New:

unsigned int chunks = (size + (bus_width - 1)) / bus_width;

In the basic dram model (dram_basic), the memory access helper uses two variables which should be unsigned ints:
Original:

int target_row = (addr>>row_bits)/num_banks;
int target_bank = (addr>>row_bits)%num_banks;

New:

unsigned int target_row = (addr>>row_bits)/num_banks;
unsigned int target_bank = (addr>>row_bits)%num_banks;
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