01-24-09-Bug 1

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This refers to the bug Fixed "issued inst not spec ready" for floating point insts (actually affected all, but only mattered in floating point cases)



Within the execution logic, the spec_ready time of a register is defined by the ready time minus the issye-to-execute delay. However, for the second source register (rs->src_physreg[1]) we were accidentally accessing the incorrect register file (floating point vs integer register file).

The original code:

if((rs->src_physreg[0] > 0)&&(my_regs.src1!=REG_NONE))
{
   cores[core_num].reg_file.reg_file_access(rs->src_physreg[0],my_regs.src1).spec_ready = cores[core_num].reg_file.reg_file_access(rs->src_physreg[0],my_regs.src1).ready - cores[core_num].ISSUE_EXEC_DELAY;
}
if((rs->src_physreg[1] > 0)&&(my_regs.src2!=REG_NONE))
{
   cores[core_num].reg_file.reg_file_access(rs->src_physreg[1],my_regs.src1).spec_ready = cores[core_num].reg_file.reg_file_access(rs->src_physreg[0],my_regs.src1).ready - cores[core_num].ISSUE_EXEC_DELAY;
}

The error is within the second register file access. "my_regs.src1" indicates which register file we use. However, my_regs.src1 applies to rs->src_physreg[0]. Therefore, we may update the spec_ready time with the ready time from the wrong register file.

The corrected code:

if((rs->src_physreg[0] > 0)&&(my_regs.src1!=REG_NONE))
{
   cores[core_num].reg_file.reg_file_access(rs->src_physreg[0],my_regs.src1).spec_ready = cores[core_num].reg_file.reg_file_access(rs->src_physreg[0],my_regs.src1).ready - cores[core_num].ISSUE_EXEC_DELAY;
}
if((rs->src_physreg[1] > 0)&&(my_regs.src2!=REG_NONE))
{
   cores[core_num].reg_file.reg_file_access(rs->src_physreg[1],my_regs.src2).spec_ready = cores[core_num].reg_file.reg_file_access(rs->src_physreg[0],my_regs.src2).ready - cores[core_num].ISSUE_EXEC_DELAY;
}
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