M-Sim is a multi-threaded microarchitectural simulation environment with
a detailed cycle-accurate model for the key pipeline structures. M-Sim
is based on SimpleScalar 3.0d.
At this point, only the Alpha AXP binaries are supported. M-Sim works
on all computing platforms which support the original SimpleScalar.
M-Sim extends the SimpleScalar 3.0d in the following ways:
- M-Sim includes cycle-accurate models for separate pipeline structures,
such as the re-order buffer (ROB), issue queue, and separate integer
and floating-point physical register files.
- M-Sim explicitly models register renaming and the associated rename
- M-Sim supports single threaded execution (superscalar mode) as well
as the multithreded mode in which multiple threads of control are executed
simultaneously, according to the Simultaneous Multithreaded (SMT) model.
In the SMT mode, some processor structures (i.e. issue queue, physical
register files, execution units, caches) are shared among the threads,
and others (rename tables, ROBs, load/store queues) are private to each
thread. For more details of the SMT model, please see the M-Sim
NEW: M-Sim Version 3.0 is now available
Version 3.0 is the third public release of the M-Sim simulation environment.
Version 2.0 was developed by Joe Sharkey, a former PhD student of Computer
Architecture and Power Aware Systems (CAPS) Research Group at SUNY
Binghamton. Version 3.0 was developed and is currently maintained by another CAPS PhD student, Jason Loew.
New in Version 3.0:
- CMP model (independent threads only) - see the wiki for usage
- Detailed modeling of pipeline flushes and register rollback
New in Version 2.0:
- Speculative scheduling based on load-latency prediction including
the squash recovery model used by the Alpha 21264 processor.
- More configurable front-end pipeline with separate stages for rename
- More detailed simulation of the issue to execute pipeline.