CS-622. Advanced Computer Architecture Seminar
Fall 2005

Instructor: Dr. Dmitry Ponomarev

Class meets: Tuesday, 6-9pm, FA 244.

Office hours: 3:00 -4:00, Tuesday & Thursday, room N-26.
Phone: (607) 777-4023
E-mail: dima at cs dot binghamton dot edu

Course Syllabus

SIMULATION TOOLS:
Aside from the traditional tools like Simplescalar, Wattch, Cacti etc., you can also try the simulators developed by the members of  our research group:

Here is the information on how to download M-Sim, the modified version of Simplescalar that implements separate structures for the key datapath components (reorder buffer, issue queue, register file), explicitly models register renaming and has support for SMT. These modifications were implemented by Joe Sharkey (jsharke@cs.binghamton.edu). M-Sim has been publicly released!  Here is the site: http://www.cs.binghamton.edu/~jsharke/m-sim

Here  is the user's manual for PTLsim, the x86-64 out of order processor simulator implemented by Matt Yourst. You should have received e-mail to the class about getting access to the code on our new x86-64 cluster; if not, ask Matt (yourst@cs.binghamton.edu).  The simulator is available at  http://www.ptlsim.org.. Also check the slides of Matt's  presentation about his simulator.

CLASS SCHEDULE:
September 6th. Topic: Data Cache Prefetching Techniques. Lecture notes
Papers:
K.Nesbit, J. Smith, "Data Cache Prefetching Using a Global History Buffer", HPCA 2004.
R. Cooksey, et.al., "A Stateless, Content-Directed Data Prefetching Mechanism", ASPLOS 2002.

September 13th. Topic: Branch Prediction
Papers:
Falcon, A., et.al., "Prophet/Critic Hybrid Branch Prediction", ISCA 2004 (Presenter - Robert)
Jimenez, D., Lin, C., "Neural Methods for Dynamic Branch Prediction", ACM Transactions on Computer Systems, 2002 (Presenter - Deniz)

September 20th. Topic: Reliability-Aware Architectures. Introduction
Papers:
Austin, T., "DIVA: A Reliable Substrate for Deep Submicron Microprocessor Design", MICRO 1999. (Presenter - Joe)
Smolens, J., et.al., "Efficient Resource Sharing in Concurrent Error-Detecting Superscalar Microarchitecture", MICRO 2004. (Presenter - Sumeet)
Qureshi, M.,et.al.,  "Microarchitecture-based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors", DSN 2005. (Presenter - Nayef)

September 27th. Topic: Reliability-Aware Architectures (continued).
Papers:
Reinhardt, S., Mukherjee, S., "Transient Fault Detection using Simultaneous Multithreading", ISCA 2000. (Presenter - Jason)
Smolens, J., et.al., "Fingerprinting: Bounding Soft Error Detection Latency and Bandwidth", ASPLOS 2004 (Presenter - Matt)
Gomaa, M., Vijaykumar, T., "Opportunistic Transient Fault Detection", ISCA 2005 (Presenter - Ehab)

October 11th. Exploiting Thread-Level Parallelism (TLP) through SMTs and CMPs - lecture.
Background papers:
Tullsen, D., et al., "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor", ISCA 1996.
Olukotun, K.,et.al.  "The Case for a Single-Chip Multiprocessor", ASPLOS 1996.
S.Adve, K.Gharachorloo, "Shared Memory Consistency Models: a Tutorial", IEEE Computer, 1996

October 18th. Issues in CMP design: memory hierarchies and interconnection networks
Papers:
Zhang, M., Asanovic, K., "Victim Replicaton: Maximizing Capacity while Hiding Wile Delay in Tiled Chip Multiprocessors", ISCA 2005 (Prateek)
Speight, E., et al., "Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors", ISCA 2005 (Hui)
Kumar, R., et al., "Interconnections in Multi-core Architectures: Understanding Mechanisms, Overheads and Scaling", ISCA 2005. (SY)

October 25th. Issues in SMT and CMP designs
Papers:
Li, Y., et.al., "Peformance, Energy and Temperature Considerations for SMT and CMP Architectures", HPCA 2005 (Dmitry)
Kirman, M., et.al., "Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors", MICRO 2005 (Deniz)
(If you have not read the original Cherry paper, here it is; make sure to read it first before you attempt to read Cherry-MP).
Kumar, R., et.al., "Conjoined Core Chip Multiprocessing", MICRO 2004. (Robert)

November 1st. Binary Translation and Dynamic Optimization Systems.
These topics will be first inroduced by Matt.
Background papers (read as many as you can):
A.Klaiber et al., "The Technology Behind Crusoe Processors", technical report.
J.Dehnert et al., "The Transmeta Code Morphing Software: Using Speculation, Recovery and Adaptive Retranslation to Address Real-Life Challenges", CGO 2003.
E.Altman et al., "BOA: The Architecture of a Binary Translation Processor", IBM Watson research report.  Here is ISCA 2004 BOA tutorial
Goldenberg et al., "IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems", MICRO 2003.

Then, Matt will present his upcoming MICRO paper
M.Yourst, K.Ghose, "Incremental Commit Groups for Non-atomic Trace Processing", MICRO 2005.

November 8th. Transactional Memory
R. Rajwar, J. Goodman, "Transactonal Lock-Free Execution of Lock-based Programs", ASPLOS 2002 (Shadi)
Hammond, L., et al., "Transactional Memory Coherence and Consistency", ISCA 2004.
McDonald, A., et al., "Characterization of TCC on Chip Multiprocessors", PACT 2005 (these two papers - Joe).
Ananian, S. et al., "Unbounded Transactional Memory", HPCA 2005. (Nayef)

November 15th. Large instruction windows and advanced speculation techniques
S. Srinivasan, et.al., "Continual Flow Pipelines", ASPLOS 2004. (Hui)
Gandhi, A., et.al., "Scalable Load and Store Processing in Latency Tolerant Processors", ISCA 2005. (Sumeet or Prateek?)
S.Sarangi, et.al., "Re-Slice: Selective Re-execution of Long-Retired Mispeculated Instructions Using Forward Slicing", MICRO 2005 (Ehab)

November 22nd. Various topics - MICRO 2005 papers
Kim, H. et al., "Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution", MICRO 2005 (Sandeep)
Barnes, R., "Flea-flicker Multipass pipelining: An Alternative to the High-Power Out-of-Order Offense", MICRO 2005 (Shadi)
Wu Q., et al., "A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance", MICRO 2005  (Jason)


November 29th. Project Presentations: Deniz, Joe, Sumeet, Prateek, Sandeep

December 6th. Project presentations: Matt, Hui, Ehab, Nayef, SY, Rob, Shadi, Jason.  Plan on giving a 15-20 min talk.