Dmitry Ponomarev

Dmitry Ponomarev

Professor and Associate Chair
Department of Computer Science
State University of New York at Binghamton
Binghamton, NY 13902-6000
Office: Q-9, Engineering Building
Phone: (607) 777-4023
E-mail: dponomar at binghamton dot edu

PUBLICATIONS
STUDENTS

ARCHITECTURE FOR SECURITY LAB

Dmitry Ponomarev is a Professor in the Department of Computer Science at SUNY Binghamton. His research interests are in the areas of computer architecture, cybersecurity, high-performance computing and parallel discrete event simulation. He published in leading conferences in these areas, including papers in ISCA, MICRO, ASPLOS, HPCA, CCS, DAC, ICCAD, ICS, PACT, IPDPS and SIGSIM-PADS. His research has been funded by the National Science Foundation, the Air Force Research Laboratory, the Air Force Office of Scientific Research and Intel. In 2016, he received SUNY Chancellor's Award for Excellence in Scholarship and Creative Activities. Four of his PhD students have been recepients of Binghamton Graduate Student Award for Excellence in Research.

Selected Recent Publications Google Scholar DBLP

Port or Shim: Stress-Testing Application Performance on Intel SGX (IISWC'20)
Demand-Driven PDES: Exploiting Locality in Simulation Models (SIGSIM-PADS'20)
LATCH: A Locality-Aware Taint CHecker (MICRO'19)
SMT-COP: Defeating Side-Channel Attacks on Execution Units in SMT Processors (PACT'19, Best paper nominee)
Controlled Asynchronous GVT: Accelerating Parallel Discrete Event Simulation on Manycore Clusters (ICPP'19)
How the Spectre and Meltdown Hacks Really Worked (IEEE Spectrum, 2019)
SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation (DAC'19)
BranchScope: A New Side-Channel Attack on Directional Branch Predictor (ASPLOS'18). CVE-2018-9056
RHMD: Evasion-Resilient Hardware Malware Detectors (MICRO'17)
RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks (DAC'17)
Covert Channels through Random Number Generator: Mechanisms, Capacity Estimation and Mitigations (CCS'16)
Jump over ASLR: Attacking Branch Predictors to Bypass ASLR (MICRO'16, selected for Top Picks in Hardware and Embedded Security Workshop at ICCAD'18)
Flexible Hardware-Managed Isolated Execution: Architecture, Software Support and Applications (TDSC'16, extended version of MICRO'14)
A Hign-Resolution Side-Channel Attack on Last-Level Cache (DAC'16, Best paper nominee)
Understanding and Mitigating Covert Channels through Branch Predictors (TACO'16)
Hardware-based Malware Detection Using Low-Level Architectural Features (TC'16, extended version of HPCA'15)

ACM SIGARCH Computer Architecture Today Blog Posts

Awards and Nominations

Binghamton University's Watson School Recognition Award for Outstanding Faculty Service, 2020
Best paper nomination, International Conference on Parallel Architectures and Compilation Techniques (PACT), 2019
MICRO'16 paper selected for presentation at Top Picks in Hardware and Embedded Security Woskshop (at ICCAD'2018).
Binghamton University's Watson School Recognition Award for Distinguished Educator, 2017
SUNY Chancellor's Award for Excellence in Scholarship and Creative Activities, 2016
Best paper nomination, Design Automation Conference (DAC), 2016
Distinguished Dissertation Award, Binghamton University, 2003
Graduate Student Award for Excellence in Research, Binghamton University, 2003
Graduate Student Award for Excellence in Teaching, Binghamton University, 2003

Research Interests

Computer Architecture
Architecture and Hardware Support for Security
High-Performance Computing

Current Courses (Fall 2020):

CS-320 Computer Systems III: Advanced Computer Architecture

Recent Program Committee Service

HPCA'21, ASPLOS'21, MICRO'20, HASP'20, IEEE MICRO Top Picks'20, HOST'20, ICPP'20, HASP'19, ISCA'19, HPCA'19, MICRO'18, ICCD'18, HOST'18, HASP'18, ICCD'17, HASP'17, HOST'17, ICCD'16, ICS'16, HASP'16, MICRO'15, ICCD'15, HASP'15, ICCD'14, ICS'13

External Review Committee Service

ISCA'20, HPCA'20, HPCA'18, MICRO'17, ISCA'17, ISCA'16, HPCA'16, ISCA'15, HPCA'15