Dmitry Ponomarev

Dmitry V. Ponomarev

Associate Professor
Department of Computer Science
State University of New York at Binghamton
Binghamton, NY 13902-6000
Office: T-20, Engineering Building
Phone: (607) 777-4023
E-mail: dima at cs dot binghamton dot edu

PUBLICATIONS
STUDENTS
CV

Selected Recent Publications Full list Google Scholar DBLP

A Non-Inclusive Memory Permissions Architecture for Protection Against Cross-Layer Attacks (HPCA'14)
SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors (IEEE TC'14)
Efficiently Securing Systems from Code Reuse Attacks (IEEE TC'14)
Exploring Many-Core Architecture Design Space for Parallel Discrete Event Simulation (SIGSIM-PADS'14)
Parallel Discrete Event Simulation for Multi-Core Systems: Analysis and Optimization (IEEE TPDS'14)
SCRAP: Architecture for Signature-Based Protection from Code Reuse Attacks (HPCA'13)
Branch Regulation: Low-Overhead Protection from Code Reuse Attacks (ISCA'12)
Non-Monopolizable Caches: Low-Complexity Mitigation of Cache Side-Channel Attacks (ACM TACO, 2012)
Optimization of Parallel Discrete Event Simulator for Multi-core Systems (IPDPS'12)
Characterizing and Understanding PDES Behavior on Tilera Architecture (PADS'12)
TPM-SIM: A Framework for Performance Evaluation of Trusted Platform Modules (DAC'11)

Research Interests

Computer Architecture
Cybersecurity
Energy-Efficient System Design
Parallel Discrete Event Simulation

Current Courses (Fall 2014):

CS-320 Computer Systems III: Advanced Computer Architecture

Professional Activities

Program Committee Member, International Conference on Computer Design (ICCD), 2014.
Program Committee Member, International Conference on Networking, Architecture and Storage (NAS), 2014.
Program Committee Member, International Conference on Supercomputing (ICS), 2013.
Program Committee Member, International Symposium on Low Power Electronics and Design (ISLPED), 2007, 2010, 2011, 2012.
Program Committee Member, International Conference on Computer Design (ICCD): 2006, 2007, 2008.
Program Committee Member, Workshop on Architectural Reliability (WAR-1), held in conjunction with MICRO, 2005 and 2006.