Dr. Dmitry Ponomarev received his M.S. degree in Computer and Information Science from SUNY Institute of Technology at Utica/Rome in 1995 and Ph.D. degree in Computer Science from SUNY Binghamton in 2003. He also received a graduate degree in Systems Engineering from Moscow Institute of Electronics and Mathematics, Moscow, Russia in 1996. His Ph.D. research was in the area of energy-efficient superscalar processor design. Dr. Ponomarev's research interests are in the area of computer architecture. His group designs energy-efficient, high-performance, complexity-effective, scalable and reliable microprocessors and memory systems.

Research Interests

Computer architecture, networking

Courses taught

• CS622 Advanced Computer Architecture Seminar (Fall 2005)
• CS522 Computer Organization and Architecture (Fall 2005)
• CS580A Advanced Topics in Computer Architecture (Spring 2004)
• CS522 Computer Organization and Architecture (Fall 2003, Fall 2004)
• CS325 Advanced Computer Organization (Spring 2001, Spring 2002, Spring 2003, Spring 2005)
• CS333 Design and Analysis of Algorithms (Fall 2000, Fall 2001, Fall 2002)

Selected Publications

• "Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch", by Joseph Sharkey and Dmitry Ponomarev, 35th International Conference on Parallel Processing (ICPP), Columbus, OH, August 2006.
• "Address-Value Decoupling for Early Register Deallocation", by Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev and Aneesh Aggarwal, 35th International Conference on Parallel Processing (ICPP), Columbus, OH, August 2006.
• "Instruction Packing: Towards Fast and Energy-Efficient Instruction Scheduling", by Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose and Oguz Ergin, ACM Transactions on Architecture and Code Optimization (ACM TACO), June 2006.
• Efficient Instruction Schedulers for SMT Processors", by Joseph Sharkey and Dmitry Ponomarev, 12th International Symposium on High Performance Computer Architecture (HPCA-12), Austin, TX, February 2006.
• "Dynamic Resizing of Superscalar Datapath Components for Energy-Efficiency" by Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose To appear in the IEEE Transactions on Computers, 2006.
• "Non-Unifirm Instruction Schedulers" by Joseph Sharkey and Dmitry Ponomarev, European Conference on Parallel Processing (Euro-Par'05), Lisbon, Portugal, August-September 2005.
• "Instruction Packing: Reducing Power and Delay of the Dynamic Scheduling Logic" by Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin, IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'05), San Diego, CA, August 2005.
• "Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure" by Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry Ponomarev 37th IEEE/ACM International Symposium on Microarchitecture (MICRO-37), Portland, OR, December 2004.
• "Reducing Datapath Energy Through the Isolation of Short-Lived Operands" by Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose 12th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT'03), New Orleans, September 2003, pp.258-268.
• "Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources" by Dmitry Ponomarev, Gurhan Kucuk and Kanad Ghose 34th IEEE/ACM International Symposium on Microarchitecture (MICRO-34), December 2001, pp. 90-101.